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Yield-improving Test and Routing Circuits for a Novel 3-d Interconnect Technology : Volume 4, Issue 9 (06/09/2006)

By Bschorr, M.

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Book Id: WPLBN0003987231
Format Type: PDF Article :
File Size: Pages 5
Reproduction Date: 2015

Title: Yield-improving Test and Routing Circuits for a Novel 3-d Interconnect Technology : Volume 4, Issue 9 (06/09/2006)  
Author: Bschorr, M.
Volume: Vol. 4, Issue 9
Language: English
Subject: Science, Advances, Radio
Collections: Periodicals: Journal and Magazine Collection, Copernicus GmbH
Historic
Publication Date:
2006
Publisher: Copernicus Gmbh, Göttingen, Germany
Member Page: Copernicus Publications

Citation

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Kohn, E., Benkart, P., Kaiser, A., Pfleiderer, H., Bschorr, M., Munding, A.,...Hübner, H. (2006). Yield-improving Test and Routing Circuits for a Novel 3-d Interconnect Technology : Volume 4, Issue 9 (06/09/2006). Retrieved from http://new.worldlibrary.net/


Description
Description: University of Ulm, Microelectronics Department, Albert-Einstein-Allee 43, 89081 Ulm, Germany. This work presents a system to increase the yield of a novel 3-D chip integration technology. A built-in self-test and a routing system have been developed to identify and avoid faults on vertical connections between different stacked chips. The 3-D technology is based on stacking several active CMOS-ICs, which have through-substrate electrical contacts to communicate with each other. The expected defects of these vias are shorts and resistances that are too high.

The test and routing system is designed to analyze an arbitrary number of connections. The result ist used to gain information about the reliability of the new 3-D processing and to increase its yield. The circuits have been developed in 0.13 μm technology, one chip has been fabricated and tested, another one is in production.

Summary
Yield-improving test and routing circuits for a novel 3-D interconnect technology

Excerpt
Abramovici, M., Breuer, M A., and Friedman, A D.: Digital Systems Testing and Testable Design, IEEE Press, New York, 1990.; Bschorr, M., Pfleiderer, H.-J., Munding, A., Kaiser, A., Benkart, P., Kohn, E., Heittmann, A., H�bner, H., and Ramacher, U.: Eine Test- und Ansteuerschaltung f�r eine neuartige 3D Verbindungstechnologie, Advanves in Radio Science, 3, 305–310, 2005.; Heittmann, A., Ramacher, U., Matolin, D., Schreiter, J., and Sch�ffny, R.: An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights, ICANN 2002 Proceedings, Madrid, Spain, 2415, 1293–1298, 2002.; Huebner, H., Eigner, M., Gruber, W., Klumpp, A., Merkel, R., Ramm, P., Roth, M., Weber, J., and Wieland, R.: Face-to-Face Chip Integration with Full Metal Interface, Proc. Advanced Metallization Conference AMC 2002, p 53, 2002.; Munding, A., Kaiser, A., Benkart, P., Bschorr, M., Heittmann, A., H�bner, H., Pfleiderer, H.-J., Ramacher, U., and Kohn, E.: Chip Stacking Technology for 3D-Integration of Sensor Systems, HETECH 2004, 13th European workshop on heterostructure technology, October 2004, Heraklion, Greece, 2004.; Schreiter, J., Ramacher, U., Heittmann, A., Matolin, D., and Sch�ffny, R.: Cellular Pulse Coupled Neural Network with Adaptive Weights for Image Segmentation and its VLSI Implementation, SPIE, San Jose (CA), USA, 5298, 290–296, 2004.

 

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